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See More Member Advantages. ATA 72R. Engine - Reciprocating. Engine - Fuel And Control. Bleed Air. Engine Controls. Engine Indicating. Turbines Reciprocating Engines. Water Injection. Accessory Gear Box Engine Driven. Propulsion Augmentation. Standard Practices - Prop. Main Rotor S. Main Rotor Drive S. Tail Rotor. Tail Rotor Drive. Rotors Flight Control. Cargo And Accessory Compartments. Serial Cables and Connectors The way SAS and SATA devices connect are through new serial connectors and cables that are much smaller and thinner, which promotes better airflow within a system.
The data and electrical connections are identical, and both reside within a single connector, although SATA also allows discrete data and power cabling, similar to a parallel ATA drive.
Figure 2: Female SAS connector. This differs from a typical SAS or SCSI connection, where an initiator and device connection is established but the connection can be temporarily discontinued to enable other traffic across the same link.
The link would then be reestablished to continue communication. Figure 3: SAS architecture model. Those applications further describe the link , although one embodiment of such link will be described below with reference to FIGS. Attention will now be focused on the downstream OSD aware shared endpoint, particularly, embodiments of the shared SATA controller What is particularly called out, however, is an arrangement by the shared SATA controller for sharing the disk drives In operation, when the processing complex executes a load instruction or otherwise performs a load operation , and the data associated with the load is not in the memory of the processing complex , the data must be retrieved from the disk s that have been configured for the processing complex In one embodiment, the operating system of processing complex transmits a read request via its link to the shared SATA controller to notify it that the processing complex requires servicing.
One skilled in the art will appreciate that other mechanisms may be used to make the shared SATA controller aware of a pending request. For example, the processing complex may simply update a pointer within the shared SATA controller to indicate that a request has been placed within memory of the processing complex , and that the shared SATA controller needs to download the request.
Further, the shared SATA controller may regularly poll memory within the processing complex to determine whether any outstanding requests exist.
One skilled in the art will appreciate that the mechanism for providing notification of an outstanding request from the processing complex to the shared SATA controller can vary with the design of the shared SATA controller , and the driver within the processing complex that talks to it.
The shared SATA controller receives the packet via its link , interprets the packet as a request for the processing complex , services the request, and provides the response to the request by embedding an association with each packet via the link or out-of-band on link Loads and stores from the other processing complexes , operate in a similar fashion. In one embodiment, the shared SATA controller may simply configure the disk drives distinctly, so that any particular drive, or set of drives, are accessed by only one processing complex Alternatively, the shared SATA controller may contain resources to allow a particular disk drive, or set of drives, to be shared as shown.
Either embodiment is contemplated by the inventor. What is particularly illustrated are two physical SATA drives to provide storage for the three processing complexes , , Array control within the shared SATA controller creates three 40 gig RAID 1 arrays , and maps the first array to processing complex , the second array to processing complex , and the third array to processing complex In the prior art illustrated in FIG.
Moreover, to provide redundancy or mirroring, each processing complex would have had to have its own SATA controller, an at least two of its own SATA drives.
However, in the example shown in FIG. What has been illustrated in FIGS. However, one skilled in the art should appreciate that the number of processing complexes, and number of SATA drives shown are exemplary only. One embodiment of the shared SATA controller of the present invention is intended to be incorporated into a blade server environment.
In today's blade environment, each blade requires its own hard drive to reside on the blade, to hold its operating system, swap space, etc. So, in an eight-blade chassis, eight hard drives are required, and eight disk controllers. None of those hard drives are hot pluggable since they are installed directly on the blade, and none of the hard disk solutions provide for any RAID configurations. Thus, if a hard drive fails on a blade, the entire blade fails.
For example, two gigabyte SATA drives could be configured in a RAID 1 configuration, and partitioned into eight 25 gig partitions, one for each of the blade servers. In this instance, full mirroring of data, which may be hot pluggable, is provided for all eight blade servers by using the shared SATA controller of the present invention, and just two SATA or serial attached SCSI drives. If one of those drives fails, the mirroring allows each of the blade servers to continue operating. The inventor believes that such an implementation is significantly more cost effective than what is known today, because of the reduction in the number of disk drives necessary to support eight blades, as well as the number of disk controllers, but also because of the increased reliability, and the reduced heat generated by the drives.
In addition, processing complex is connected to processing complex via a link This embodiment is shown to illustrate a redundant, or mirrored pair of processing complexes or servers executing the same operating system, instructions, etc.
However, the prior art would have each of the processing complexes , coupled to their own SATA controller, and their own disk drives. But, by utilizing the shared aspect of the present invention, an improvement is made as will now be addressed. One skilled in the art will appreciate that the array configuration of disk drives to the processing complex is not the important issue.
Rather, it is the sharing of the shared SATA controller by multiple processing complexes to which the invention is directed. However, in the mirrored configuration illustrated in FIG. In one embodiment, if processing complex fails, processing complex is alerted of the failure via link When processing complex recognizes that processing complex has failed, it would be advantageous for it to be able to perform stores not only to the disk drives that are configured for it, but also for the disk drives that have previously been allocated to the processing complex Processing complex communicates to the shared SATA controller that processing complex has failed, and that it now wishes to perform any stores to its array, and to the array previously configured for processing complex Thus, the shared SATA controller can now perform the writes to both sets of disk drives on behalf of processing complex That is, reads could effectively be provided to the processing complex by its array, and by the array previously configured to support processing complex , thereby doubling load performance from the disk drives.
Without the ability to share the shared SATA controller , the inventor is unaware of any way to provide this configuration. What should be appreciated in FIG. Rather, it is the ability to share an endpoint, such as the shared SATA controller, via an OSD aware link or non OSD aware link along with an out-of-band association link to which the invention is directed.
The purpose of this logic is to view incoming packets, and determine which upstream OSD is associated with the packets. The OSD ID logic is also responsible for associating response packets with their upstream requester. How the core logic performs these various functions will now be described. Within the core logic is one or more task files The purpose of the task file s is to store tasks generated by the OSD's or processing complexes as described above.
However, within the shared SATA controller of the present invention, it is necessary to associate outstanding tasks with their originating OSD. This can be accomplished in many ways. In an alternative embodiment, one or more task files are provided which contain memory space to store an OSD TAG for outstanding tasks.
Thus, rather than storing tasks in separate task files i. One skilled in the art will appreciate that it is not the structure of the task file that is important. Moreover, it should be appreciated that the shared SATA controller of the present invention need not necessarily increase the size of the task file s That is, the size of the task file s is not dependent on the number of OSD's supported by the shared SATA controller , but rather on the performance specified by the designer.
Thus, in one embodiment, the task file could be a single register, operating on one task at a time. Or, in an alternative embodiment, the task file could be designed to accommodate a static number of outstanding tasks from the multiple OSD's. In this embodiment, arbitration logic would be used to manage fairness of task file resources to the OSD's, and arbitrate between existing tasks in the task file Another embodiment envisions dynamic allocation of a memory, such as the memory for use as a task file as needed from moment to moment by the OSD's.
All such configurations are envisioned by the present inventor. The core logic further includes one or more sets of control registers In a non-shared SATA controller, two sets of control registers are provided to provide communication with its processing complex.
The second set of control registers are specific to the controller, and are particular to the OSD supported. It is common in controllers today to implement these registers using flip flops to allow for quick response. In addition, some of the second set of control registers are common to all OSD's and some are specific to each OSD supported. The present invention allows the control registers which is inclusive of both sets of control registers discussed above to be implemented in flip flops.
However, because of the potential die size impact of increasing the control registers per OSD, a portion of the memory is used to store OSD specific control registers. In an alternative embodiment, off controller memory is further utilized to store increased number of control registers to support additional OSD's. One skilled in the art will appreciate that the number of OSD's supported by the shared SATA controller , and the architecture of additional control registers is strictly a design concern, with respect to die size impact and performance.
The necessary additional control registers to support multiple OSD's can be made by increasing the number of control registers , by allocating a portion of the memory to store additional control register information on the controller , by utilizing off controller memory , or any combination thereof.
The task file s are shown coupled to one or more DMA engines It is contemplated that the number of DMA engines provided within the shared SATA controller are dependent on the performance desired by the manufacture, but should not be necessarily related to the number of processing complexes or OSD's supported. It is the responsibility of the core logic , and particularly the arbitration logic , to provide arbitration of the DMA engines for requests from the multiple OSD's.
Within the DMA engines are timing logic and request tables In one embodiment, the timing logic monitors outstanding requests, per OSD, to insure that pending requests are terminated in a timely fashion.
For example, if a request to a particular OSD does not receive a response, other requests should not be held up indefinitely. Rather, the request should be cancelled, and reported to the OSD, to allow other requests to proceed. Further, if a determination is made by the DMA engines that an OSD is not responding, all pending requests within the task file should be cancelled.
The DMA engine s also contain one or more lookup tables to associate outstanding requests with particular OSD's. Within a non shared environment, pending requests are tagged so that responses can be related to their associated request. However, within the shared environment of the present invention, in addition to tagging outstanding requests with a request identifier, the requests are also tagged with their associated OSD.
This is necessary because it is possible for requests from different OSD's to have the same request identifier. As mentioned above, the number of DMA engine s provided, and the number of outstanding requests each are capable of, is a design consideration respecting performance. Alternatively, a shared SATA controller may be built with multiple DMA engines , each of which is capable of having multiple outstanding requests. Any combination is envisioned by the present inventor.
The DMA engine s are shown coupled to one or more memories Or, alternatively, memory space could be provided to support DMA activity for all OSD's by providing an OSD tag for each request, response and data, and placing such requests, responses, data for all OSD's within a common memory The arrangement of the memory , or its location, are not important to the present invention.
The core logic also contains one or more array control and partitioning logic blocks As mentioned above, it is contemplated that within the shared SATA controller , it may be configured to support one or more processing complexes or OSD's , each of which may have one or more sets of disk drives configured in an array. That is, there need not be a direct correlation between the number of OSD's supported by the shared SATA controller , and the number of array control logic blocks For example, a single physical drive may be dedicated to a single OSD, either as a physical drive, or as part of an array.
Alternatively, a single physical drive may be partitioned into two or more virtual drives, each of which may then be presented as a physical drive to an OSD, or as part of an array to an OSD.
For example, referring briefly back to FIG. Drive B however is partitioned into two virtual drives. The first virtual drive is presented to array control block to be used in the RAID 0 array created for processing complex The second virtual drive for physical drive B is presented to the array control block or a second array control block to be used as one of the three drives in the RAID 5 configuration for processing complex Drive C is partitioned into two virtual drives.
The first virtual drive within physical drive C is presented to array control as one of the three drives for the RAID 5 configuration for processing complex The second virtual drive within physical drive C is presented to array control as one of two drives for the RAID 1 array for processing complex Drive D is partitioned into two virtual drives.
The first virtual drive within physical drive D is presented to array control as one of the three drives for the RAID 5 configuration for processing complex The second virtual drive within physical drive D is presented to array control as one of the two drives for the RAID 1 array for processing complex Thus, referring back to FIG.
For example, in FIG. Operationally, when a request comes into the shared SATA controller to perform a write to logical drive 1, the array control and partitioning will examine the OSD tag for the request, determine whether the request is from OSD 1 , or OSD 2 , and then cause the request to be presented to the appropriate physical drive based on that mapping. Further, within the array control and partitioning logic is one or more link queue's , which may or may not have an OSD tracking field
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